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The gated clock technique is discussed and used to instruct the microarchitecture partition.
发展了门控时钟理论，讨论了门控时钟对系统划分的影响。
参考来源 - 行为逻辑层上的SOC低功耗设计Low-power processor most adopt the system-level design, the technologies include: reconfigurable dynamic cache and cache closed, gated clock technology, dynamic voltage scaling DVS technology, multi-core technology.
处理器的低功耗设计大都采用系统级,其技术主要包括:可重配置的cache及动态关闭cache技术,门控时钟技术,动态电压缩放DVS(dynamic voltage scaling)技术,多核技术等。
参考来源 - 嵌入式系统的低功耗研究·2,447,543篇论文数据，部分数据来源于NoteExpress
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
Many go to live in one of the increasingly popular fortress-like gated communities, protected around the clock by armed guards.
许多人倾向于居住在日益兴盛的堡垒式社区内，这些社区有24小时的安保服务。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
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